1. Field of the Invention
The present invention relates to a semiconductor device, and to a method for manufacturing the same. In particular, the present invention relates to a Dynamic Random Access Memory (DRAM) semiconductor device that has a Capacitor Over Bitline (COB) structure.
2. Description of the Related Art
DRAMs are used as conventional memory devices for computers, printers, etc. A Capacitor Over Bitline (COB) structure is commonly used to achieve miniaturization of such DRAM circuits. In the COB structure, a capacitor of a memory cell is formed over a bit line to thereby reduce an area of the memory cell.
In the semiconductor device having a COB structure, a conductive layer which forms a capacitor electrode is also used to form a resistance of a peripheral circuit. FIG. 12(a) is a cross sectional view of a memory cell 10 of a conventional semiconductor device, and FIG. 12(b) is a cross sectional view of the peripheral circuit. The semiconductor device has a capacitor 16, which includes a lower electrode 16a, an upper electrode 16b, and a capacitor insulating layer 16c, as shown in FIG. 12(a). The semiconductor device further has a first conductive layer 18, a second conductive layer 20, a third conductive layer (not shown in FIG. 12), a first intermediate insulating layer 26, a second intermediate insulating layer 30, a barrier metal layer 36, and an interconnection layer 38 as shown in FIGS. 12(a) and 12(b). A fourth conductive deposition layer 16b, which is made of a polysilicon, forms the upper electrode 16b of the capacitor 16, as well as resistance in the peripheral circuit. While the upper electrode 16b and the resistance are not connected, they are formed by the same deposition process and are thus contained in the same deposition layer.
The interconnection layer 38 is electrically connected to the resistance of the fourth conductive layer 16b via a contact hole 34 located at the peripheral circuit. A top surface of the second intermediate insulating layer 30 at the contact hole is flattened, as shown in FIG. 12(b). The thickness of this portion of the second intermediate insulating layer 30, where the interconnection 38 is connected, is thinner than other portions thereof due to an uneven surface of the first intermediate insulating layer 26. That is, a convex portion is caused in the first intermediate insulating layer 26 due to the second conductive layer 20.
If an aspect ratio of the contact hole 34 becomes smaller, a problem arises as described below with respect to FIGS. 13(a) and 13(b).
A barrier metal layer 36, which is a titanium nitride (TiN) in this example, is formed over the contact hole 34, as shown in FIG. 13(b). A metal layer (Ti layer) 36a is formed over the resistance (fourth conductive layer 16b) and the second intermediate insulating layer 30 as shown FIG. 13(a). Then, a Rapid Thermal Nitridation (RTN) is performed. The surface barrier metal layer (Ti layer) is nitrided during the RTN. However, some titanium silicide is formed at a connecting portion between the barrier metal layer (Ti) and the polysilicon of the fourth conductive layer 16b. About 20˜25% of a volume of the polysilicon is decreased at the connecting portion due to the formation of the titanium silicide. Therefore, a hollow portion 40 is formed under the contact hole 34 as shown in FIG. 13(b). The hollow portion increases a resistance between the interconnection 38 shown in FIG. 12(b) and the fourth conductive layer 16b. In the case where the aspect ratio is smaller than 0.6, a thick barrier metal (Ti) layer 36 is formed at the bottom of the contact hole 34. This problem often occurs when the thick barrier metal (Ti) layer is formed at the bottom of the contact hole 34.